1. Field of the Invention
The present invention relates generally to clock generation circuitry and, in particular, the clock generation which includes duty cycle control.
2. Description of Related Art
There are many applications for clock generation circuitry. In some instances, the clock produced by such circuitry must have a very precise duty cycle. The usual definition of duty cycle is the ratio of the clock high period to the total clock period in terms of percentage. One problem frequently encountered in oscillator and clock generator design is the difficulty in obtaining a symmetrical duty cycle of 50%, which is clock having equal high and low periods. This is particularly true when an odd integer divider is involved. Various circuits and methods have been proposed to address these issues. As will be seen, many of the solutions may provide acceptable performance in some circumstances but are not able to accommodate the precision and wide dynamic rage required in certain applications such as clock drivers used for switching DC to DC converters used in modern integrated power management systems.
Generally, previous designs for duty cycle control utilize a digital delay line approach or an analog delay line approach. Referring to the drawings, FIG. 1 is a simplified diagram of an exemplary prior art clock generator circuit utilizing a digital delay line which is configured to produce a nominal 50% duty cycle which can be varied in a somewhat controlled manner. FIG. 2 is a related timing diagram. Further details of the circuit are disclosed in U.S. Pat. No. 6,822,497, the contents of which are fully incorporated herein by reference. Clock Fin shown in FIG. 2 is provided by an oscillator or other clock generator 20. It can be seen from waveform 28A that the duty cycle of Fin is substantially less than 50%.
Clock Fin and a delayed version DFin (waveform 28B) are coupled to the S and R inputs of a latch 24. The output clock Fout having the controlled duty cycle is produced as the Q output of latch 24. A current controlled delay circuit 22 provides a delay D to produce DFin. In order to provide a nominal 50% duty cycle, delay D has a duration equal to one-half the period of clock Fin. Delay circuit 22 typically includes one or more CMOS gates, having a controllable power supply current which alters the propagation delay through the gates. These delay gates may be followed by R and C elements. In this case, the value of delay D can be altered over a given range by controlling the current through line 32 connected to the power source for the delay gates. The rising edge 34A of clock Fin triggers a one shot within latch 24 to produce a narrow pulse that will set the latch output Q to a high state. The rising edge 34B of delay clock DFin also triggers a one shot within latch 24 which resets the latch causing Fout to switch back to a low state.
A delay setting circuit 30 produces a current on line 32 for setting the duty cycle of Fout. In addition, a duty cycle converter 26 provides a fed back correction current on line 32 to maintain the duty cycle at the desired point. Circuit 26 typically includes a pair of equal current sources, with a first current source charging a capacitor when Fout is in a first state and with the second current source discharging the capacitor when Fout is in a second state, with the voltage on the capacitor representing the duty cycle. Converter 26 produces a correction current on line 32 from the duty cycle voltage on the capacitor which is also indicative of the sensed duty cycle. This correction current in combination with the primary current provided by the current produced by circuit 30 operates to maintain Fout at the desired duty cycle.
FIGS. 3 and 4 illustrate a further approach to producing a clock having a precise duty cycle. Generally, an analog pulse reshaping monostable multivibrator scheme is employed. Further details of this approach are set forth in U.S. Pat. No. 7,123,179, the contents of which are fully incorporated herein by reference. An oscillator circuit 36 produces a clock Fin having a duty cycle in this example of significantly less than 50% (FIG. 4). The rising edge of Fin triggers a one shot 38 that produces a relatively narrow pulse that operates to momentarily turn ON a transistor 40 so as to discharge a capacitor C1. When the pulse terminates, transistor 40 is turned OFF so that a current source 42 can charge capacitor C1 thereby producing a ramp voltage Ramp at the positive input of a comparator 44. The other input to comparator 44 is a voltage Vref to be described.
Comparator 44 produces the clock output Fout. A duty cycle to voltage converter circuit 46 splits Fout into two channels 48A and 48B. The input of channel 48A has an exclusive OR circuit (a high output is produced when the inputs differ), with one input for receiving Fout and the other input connected to a logic “0”. The result is Fout+ shown in FIG. 4 which is in phase with Fout. The input of channel 48B also has an exclusive OR circuit with one input for receiving Fout and the other input connected to a logic “1”. The result is Fout− shown in FIG. 4 which is out of phase with respect to Fout and Fout+. Circuit 48A includes an RC circuit which operates to integrate Fout− to provide a voltage Vavg1 at node 50A indicative of the duration of the high state of Fout−. Similarly, circuit 48B includes an RC circuit which operates to integrate Fout+ to produce a voltage Vavg2 at node 50B indicative of the high state of Fout+.
An error amplifier 52 provides an output Vref indicative of the difference between Vavg1 and Vavg2 which is filtered by a capacitor C2. Voltage Vref is also indicative of the duty cycle of Fout. If Vavg1 and Vavg2 are equal, the duty cycle is 50%. An offset circuit 52 can be used in one of the channels (Fout+ in this case) to provide an adjustable offset for target duty cycles other than 50%. Comparator 44 changes state when voltage Ramp has increased to Vref, thereby producing a falling edge on Fout. Feedback of voltage Vref tends to maintain Fout at the desired duty cycle.
The above described exemplary approaches for providing an output clock having a controlled duty cycle are adequate under many operating conditions. However, shortcomings exist limiting their use in certain high performance applications. As will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention, the present invention addresses many of those shortcomings.